Field effect transistor (fet) with self-aligned contacts, integrated circuit (ic) chip and method of manufacture

ABSTRACT

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.

CROSS REFERENCE TO RELATED APPLICATION

The present invention is a divisional of U.S. patent application Ser. No. 13/956,339 (Attorney Docket No. YOR920130074US1), “FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE” to Szu-Lin Cheng et al., filed Jul. 31, 2013, assigned to the assignee of the present invention and incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor Field Effect Transistor (FET) manufacture and more particularly to improving yield and reliability in semiconductor chip manufacture.

2. Background Description

Integrated Circuits (ICs) are commonly made in the well-known complementary insulated gate Field Effect Transistor (FET) technology known as CMOS. Typical high performance ICs include CMOS devices (FETs) formed in a number of stacked layers (e.g., wiring, via, gate and gate dielectric) on a surface semiconductor (silicon) layer of a Silicon On Insulator (SOI) chip or wafer. CMOS technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). In what is typically referred to as scaling, device or FET features are shrunk to shrink corresponding device minimum dimensions, including both horizontal dimensions (e.g., minimum channel length) and vertical dimensions, e.g., channel layer depth, gate dielectric thickness, junction depths and etc. Shrinking device size increases device density and improves circuit performance (both from increased device drive capability and decreased capacitive load).

With scaling, however, what had become small, insignificant and neglectable defects have become significant, to the point of causing chip failures and negatively impacting yield. Scaling has made forming electrical contacts to device source/drain regions, especially for what are known as raised source/drain devices, for example, a considerable challenge. Typically, contacts are formed after opening (smaller and smaller) contact openings or vias through an insulation layer to the device raised source/drains, e.g., using a reactive ion etch (RIE) self-aligned contact, and filling the openings with a conductive material. However, using conventional contact oxide RIE for self-aligned contacts erodes device sidewall spacers that causes gate to source /drain shorts. These shorts have caused a significant drop in chip yield.

Thus, there exists a need for improved self-aligned source/drain contact formation in semiconductor manufacturing, and more particularly; there exists a need for self-aligned source/drain contact formation that does not incur sidewall spacer loss at contact oxide while avoiding source/drain contact to device gate shorts to improve chip yield and reliability.

SUMMARY OF THE INVENTION

An aspect of the invention is improved contact formation in semiconductor manufacturing;

Another aspect of the invention is improved self-aligned raised source/drain (RSD) contact formation in semiconductor manufacturing;

Yet another aspect of the invention is self-aligned raised source/drain (RSD) contact formation that does open contact insulator using RIE and, therefore, does not incur sidewall spacer loss at contact oxide, and further avoids source/drain contact to device gate shorts for improved chip yield and reliability.

The present invention relates to a Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Raised source/drains are formed in source/drains regions. A stopping layer is formed on raised source/drains. Contact spacers are formed above gates, e.g., through a sacrificial layer. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

FIG. 1 shows an example of steps in a method for forming device contacts according to a preferred embodiment of the present invention;

FIGS. 2A-B show an example of a typical wafer and a cross section of the wafer, with chips manufactured on the wafer;

FIG. 3 shows a cross sectional example of device locations defined on a typical layered wafer;

FIGS. 4A-B a cross sectional example after forming raised source/drains;

FIG. 5 an example of a stopping layer is formed on the raised source/drains;

FIGS. 6A and B show an example of source/drain contact spacer formation;

FIGS. 7A-B show an example of siliciding the raised source/drains;

FIG. 8 show an example of source/drain contacts are on the silicided source/drains and separated by the contact spacers.

DESCRIPTION OF PREFERRED EMBODIMENTS

Turning now to the drawings and, more particularly, FIG. 1 shows an example of forming 100 source/drain device contacts to semiconductor Field Effect Transistors (FETs), both N-type FETs (NFETs) and P-type FETs (PFETs), according to a preferred embodiment of the present invention. Preferably, the FETs are Raised Source/Drain (RSD) devices in Integrated Circuit (IC) chips formed in the complementary insulated gate technology, commonly referred to as CMOS. Preferably also, the CMOS IC chips are formed on a semiconductor wafer, e.g., a Silicon On Insulator (SOI) wafer. Devices with self-aligned source/drain contacts thus formed avoid spacer loss at contact oxide to prevent lateral shorts that might otherwise occur and improve manufacturing yield and chip reliability.

It is understood that although described in terms of CMOS SOI for example only. The present invention has application to any suitable semiconductor IC material. Thus, the semiconductor wafer may be a bulk semiconductor wafer. Further, the SOI wafer semiconductor substrate may be any suitable III/V semiconductor material or compound such as, for example, silicon (Si), germanium (Ge), SiGe, silicon Carbon (SiC), SiGeC, Gallium Arsenide (GaAs), Indium Phosphorous (InP), InAs, or any combination thereof in a single layer or in a multilayer structure. The insulating layer may be, for example, an oxide or nitride in crystalline or non-crystalline form.

Fabrication begins 102 with a layered wafer and defining 104 device locations on the wafer. Locations may be defined by forming FET gates on the wafer and opening the surface layer to define device areas for P-type and N-type devices, e.g., for Shallow Trench Isolation (STI). Source/drain regions, e.g., for Raised source/drain (RSD), are re-formed 106 adjacent to the FET gates. Next a stopping layer is formed 108 on the source/drain regions. Source/drain contact spacers are formed 110, e.g., above the FET gates to separate subsequently formed source/drain contacts. Silicide is formed 112 on the source/drain regions, e.g., by converting the stopping layer. Source/drain contacts are formed 114 on the silicided the source/drain regions separated by the contact spacers. Finally, normal IC chip fabrication continues normally 116, connecting devices together to form circuits and wiring circuits together to form chips.

FIGS. 2A-B show an example of a typical wafer 120 and a cross section of the wafer 120 through B-B. In the example of FIG. 2A chips 122 are manufactured on the wafer 120 according to a preferred embodiment of the present invention. Metal lines on upper layers wire chip FETs into chip circuits and wire chip circuits together. One or more of the connected circuits includes at least one preferred FET.

As shown in the cross section of FIG. 2B, a typical layered provided in 102 in FIG. 1, such as wafer 120, includes a substrate 124 supporting an insulating layer 126. The insulating layer 126 supports, and is sandwiched between, a surface semiconductor layer 128 and substrate 124. Preferably, the surface semiconductor layer 128 is a silicon layer of a Silicon on Insulator (SOI) wafer 120. Preferably also, the insulating layer 126 is a buried oxide (BOX) layer.

FIG. 3 shows a cross sectional example of device locations 130, 132 defined on the typical layered wafer, e.g., wafer 120 in FIGS. 2A-B with like features labeled identically. Device location definition (104 in FIG. 1) begins by defining islands 134, 136 in the surface layer. Preferably, a typical shallow trench isolation (STI) technique opens trenches that define the surface layer islands 134, 136 and filling the trenches with insulator 138. Island definition is followed by implanting with a channel tailoring implant, P-type in NFET locations 130 and N-type in PFET locations 132. Alternately, channel implant may be done before segmenting the surface layer.

Device gate 140 formation begins with a gate dielectric layer, less than 20 nm thick depend in on the selected dielectric material, formed on the surface layer 128. A gate layer, 50-150 nm thick, is formed on the gate dielectric layer. Gates 140 are patterned, e.g., using typical state of the art photolithographic patterning (mask and etch) techniques. The gate dielectric, e.g., HfO₂, Al₂O₃ or SiO₂, may be patterned with, before or after patterning the gates 140. Preferably, patterning is done with a hard mask of a dielectric material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, silicon boron nitride or multilayered stacks thereof.

After the gates 140 are patterned, source/drain regions 142, 144 are defined on both sides of the gates 140. Gate caps 146 cap and enclose the gates 149. Preferably the gate caps 146 are a suitable dielectric less than 30 nm wide and preferably 5 nm wide, and formed on and along both sides of the gates 140. Gate caps 146 may be formed, for example, by forming a conformal layer of dielectric material over the gates 140 and patterning photolithographically. The dielectric material may be, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, silicon boron nitride or a multilayered stack thereof. Alternately, the gate caps 146 may be formed by forming a capping layer on the gate and sidewall spacers, e.g., after forming a conformal dielectric layer and a reactive ion etch (RIE) to re-expose the doped island surface 148, 150 in regions 142, 144. Thus, depending on the material(s) used, gate caps 146 may be a uniform single material or two or more materials, i.e., sidewall spacers and caps. Optionally, the gates 140 may be metal gates formed using a typical state of the are replacement gate technology. are formed to mask the top of gates 140

Next in FIGS. 4A-B raised source/drains are formed (106 in FIG. 1) in source/drains regions 142, 144. First, the exposed island surfaces 148, 150 are sub-etched, preferably, 15 nm, exposing channel sidewalls 152 in trenches 154, 156. Then, semiconductor 158, 160 is grown epitaxially in, and refilling, trenches 154, 156. Preferably, in situ phosphorous doped (ISPD) silicon (Si) 158 is grown to fill and extending above the NFET source/drain trenches 154, preferably by 30 nm; and, in situ boron doped (ISBD) silicon Germanium (SiGe) 160 is grown to fill and extending above the PFET source/drain trenches 156, preferably also by 30 nm.

In FIG. 5 stopping layer 162 is formed 108 on the raised source/drains 158, 160. Preferably, the stopping layer 162 is a 1-5 nm thick silicon layer, nominally 1 nm thick, grown doped or undoped on the Si and SiGe raised source/drains 158, 160. It should be noted that the stopping layer 162 merges with source/drain silicon in NFET areas, but remains a separate layer on SiGe raised source/drains 160 in PFET areas.

FIGS. 6A and B show source/drain contact spacer formation, 110 in FIG. 1. First a sacrificial layer 164 is grown on the stopping layer 162. Preferably, the sacrificial layer 164 is SiGe grown selective to the stopping layer 162, such that the SiGe is thick enough that the upper surface is at least 5 nm above the gate caps 146. After stopping layer 162 formation, contact spaces 166 remain open, or are opened, above each gate 140. Stopping layer 162 formation may stop before the layer 162 covers the gate caps 146. Alternately, the contact spaces 166 may be opened, e.g., using typical state of the art mask and etch (e.g., RIE). Since sacrificial layer 164 forms only on the stopping layer 162, contact spaces 168 remain open above shallow trenches 138.

The contact spaces 166, 168 are filled with insulator 170, preferably oxide. Oxide may be deposited on the patterned sacrificial layer 164, and filling the contact spaces 166, 168. Then excess oxide is removed from above, and to, the patterned sacrificial layer 164. For example, a typical chemical-mechanical (chem-mech) polish (CMP) may be used to remove excess dielectric and re-planarize the wafer surface to the patterned sacrificial layer 164. After CMP only contact spacers 170 insulator remains, i.e., the insulator that fills the contact spaces 166, 168.

It should be noted that the sacrificial layer 164 may be a uniform layer or multiple layers of any suitable material, semiconductor, insulating material or conductive material. However, the material must be selected to have an etch rate with a suitable etchant (selective to the sacrificial material) that is different than the stopping layer 162 and the contact spacers 170. In particular the selected material can be doped or undoped germanium, or a semiconductor material that includes doped or undoped germanium, e.g., a silicon germanium (Si_(x)Ge_(y)) alloy where x=0.20-0.9999 (20-99.99% by weight) and y<=1−x.

FIGS. 7A-B show forming silicide (112 in FIG. 1) on the raised source/drains 158, 160. First, the patterned sacrificial layer 164 material is removed, e.g., using a suitable wet etch that is selective to SiGe. Removing the patterned sacrificial layer 164 re-exposes, and stops on, the stopping layer 162. Then, the stopping layer is converted to silicide 162′ on each of the raised source/drains 158, 160.

For example, a highly selective etch can remove the sacrificial material without etching, or only minimally, the stopping layer 162 and contact spacers 170. A typical RCA clean may be used for preparing a germanium-containing sacrificial material, and a Si stopping layer. Alternately, instead of cleaning the wafer in an RCA clean, the sacrificial material may be etched away to the stopping layer 162 in hydrochloric acid (HCl) vapor at 300°-750° C., and preferably at 600° C.

In FIG. 8 source/drain contact spacers 170 act as a mold for source/drain contacts 172, formed (114 in FIG. 1) on the silicided raised source/drains 158, 160. Preferably metal, e.g., tungsten (W), is deposited on the wafer 120 and planarized to the top of contact spacers 170. Tungsten, for example, may be deposited and partially etched back using a RIE, followed by CMP to complete excess metal removal and replanarize the wafer 120. Once the contacts 172 are complete, IC chip fabrication continues normally 116, forming subsequent, upper level wires connecting devices together to form circuits and wiring circuits together to form chips.

Thus advantageously, self-aligned raised source/drain (RSD) contacts form without using RIE to open contact insulator. Therefore, RSD devices thus formed do not incur sidewall spacer loss at contact oxide, and further avoid source/drain contact to device gate shorts for improved chip yield and reliability.

While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. It is intended that all such variations and modifications fall within the scope of the appended claims. Examples and drawings are, accordingly, to be regarded as illustrative rather than restrictive. 

What is claimed is:
 1. A method of forming Field Effect Transistors (FETs), said method comprising: defining FET locations on a semiconductor wafer; forming gates in said FET locations source/drain regions being defined adjacent to said gates; forming source/drains in said source/drain regions; forming a stopping layer on said source/drains; forming contact spacers above said gates; and forming source/drain contacts to said stopping layer.
 2. A method of forming CMOS Integrated Circuit (IC) chips, said method comprising: defining Field Effect Transistor (FET) locations on a semiconductor wafer; forming gates in defined said FET locations; forming source/drains adjacent to said gates; forming a stopping layer on said source/drains; forming contact spacers above said gates; converting said stopping layer to silicide; forming source/drain contacts to the silicided source/drains; and forming chip wiring connecting said FETs into chip circuits and connecting said chip circuits together.
 3. A Field Effect Transistor (FET) comprising: a semiconductor island in a surface of a semiconductor wafer; a gate on a channel in said semiconductor island; a dielectric cap encasing said gate on said semiconductor island; a source/drain at said each end of said channel, each said source/drain having an upper surface above a lower surface of a respective said gate; an insulating spacer above said gate on said dielectric cap; and source/drain contacts self-aligned to said FET, said insulating spacer separating said self-aligned source/drain contacts.
 4. A FET as in claim 3, wherein said semiconductor wafer is a silicon on insulator (SOI) wafer, said surface is a surface silicon layer, said FET further comprising a silicide layer on each said raised source/drain.
 5. A FET as in claim 4, wherein said FET is a NFET and said each raised source/drain is phosphorous doped silicon (Si).
 6. A FET as in claim 4, wherein said FET is a PFET and said each raised source/drain is boron doped silicon germanium (SiGe).
 7. A FET as in claim 4, wherein said FET is one of a plurality of FETs on a CMOS Integrated Circuit (IC) chip, said plurality of FETs being connected together into chip circuits by chip wiring, said chip wiring connecting said chip circuits together.
 8. A CMOS Integrated Circuit (IC) chip comprising: a plurality of silicon islands in a surface silicon layer of a silicon on insulator (SOI) wafer, said plurality of silicon islands including a plurality of NFET islands and a plurality of PFET islands; at least one gate on each NFET island and each PFET island; a dielectric cap encasing each said at least one gate above a channel; a raised source/drain at said each end of said channel, each said raised source/drain having an upper surface above an upper channel surface; a silicide layer on each said raised source/drain; self-aligned contacts to said source/drain regions; an insulating spacer above said each at least one gate on said dielectric cap, said insulating spacer separating said self-aligned contacts; and chip wiring connecting IC chip NFETs and PFETs into IC chip circuits and connecting said IC chip circuits together.
 9. A CMOS IC as in claim 8, wherein for each NFET each raised source/drain is phosphorous doped silicon (Si); and, for each PFET each raised source/drain is boron doped silicon germanium (SiGe). 